Commit 1fc6619e authored by Xiang Li's avatar Xiang Li

Merge branch 'comp1' into 'master'

Fix compiler errors when SIMD_ENABLE is set to 0

See merge request jvet/VVCSoftware_VTM!527
parents 9d0f0ac5 67e61ac5
Pipeline #1490 passed with stage
......@@ -42,11 +42,6 @@
#include "Buffer.h"
#include "InterpolationFilter.h"
#if ENABLE_SIMD_OPT_BUFFER
#ifdef TARGET_SIMD_X86
#include "CommonDefX86.h"
template< typename T >
void addAvgCore( const T* src1, int src1Stride, const T* src2, int src2Stride, T* dest, int dstStride, int width, int height, int rshift, int offset, const ClpRng& clpRng )
{
......@@ -298,9 +293,6 @@ PelBufferOps::PelBufferOps()
PelBufferOps g_pelBufOP = PelBufferOps();
#endif
#endif
void copyBufferCore(Pel *src, int srcStride, Pel *dst, int dstStride, int width, int height)
{
int numBytes = width * sizeof(Pel);
......
......@@ -51,16 +51,15 @@
// AreaBuf struct
// ---------------------------------------------------------------------------
#if ENABLE_SIMD_OPT_BUFFER
#ifdef TARGET_SIMD_X86
struct PelBufferOps
{
PelBufferOps();
#if ENABLE_SIMD_OPT_BUFFER && defined(TARGET_SIMD_X86)
void initPelBufOpsX86();
template<X86_VEXT vext>
void _initPelBufOpsX86();
#endif
void ( *addAvg4 ) ( const Pel* src0, int src0Stride, const Pel* src1, int src1Stride, Pel *dst, int dstStride, int width, int height, int shift, int offset, const ClpRng& clpRng );
void ( *addAvg8 ) ( const Pel* src0, int src0Stride, const Pel* src1, int src1Stride, Pel *dst, int dstStride, int width, int height, int shift, int offset, const ClpRng& clpRng );
......@@ -84,10 +83,6 @@ struct PelBufferOps
extern PelBufferOps g_pelBufOP;
#endif
#endif
void paddingCore(Pel *ptr, int stride, int width, int height, int padSize);
void copyBufferCore(Pel *src, int srcStride, Pel *Dst, int dstStride, int width, int height);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment