From 30e73fce4727b08b7000b9fe8211929f85bcf3de Mon Sep 17 00:00:00 2001
From: Ryoji HASHIMOTO <ryoji.hashimoto.te@renesas.com>
Date: Wed, 26 Jun 2019 18:13:35 +0900
Subject: [PATCH] Fix for ticket 230, wrong memory bandwidth in DMVR Cache is
enabled incorrectly in DMVR processing
---
source/Lib/CommonLib/InterPrediction.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/source/Lib/CommonLib/InterPrediction.cpp b/source/Lib/CommonLib/InterPrediction.cpp
index a8681152c6..e7e6cb5f18 100644
--- a/source/Lib/CommonLib/InterPrediction.cpp
+++ b/source/Lib/CommonLib/InterPrediction.cpp
@@ -741,7 +741,7 @@ void InterPrediction::xPredInterBlk ( const ComponentID& compID, const Predictio
JVET_J0090_SET_CACHE_ENABLE( false );
m_if.filterVer(compID, (Pel*)tmpBuf.buf + ((vFilterSize >> 1) - 1) * tmpBuf.stride, tmpBuf.stride, dstBuf.buf, dstBuf.stride, backupWidth, backupHeight, yFrac, false, rndRes, chFmt, clpRng, bilinearMC, bilinearMC);
}
- JVET_J0090_SET_CACHE_ENABLE( true );
+ JVET_J0090_SET_CACHE_ENABLE( srcPadStride == 0 ); // Enabled only in non-DMVR process, In DMVR process, srcPadStride is always non-zero
if (bioApplied && compID == COMPONENT_Y)
{
const int shift = std::max<int>(2, (IF_INTERNAL_PREC - clpRng.bd));
--
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