Fix mem band cache enable in dmvr
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@@ -741,7 +741,7 @@ void InterPrediction::xPredInterBlk ( const ComponentID& compID, const Predictio
Fix memory bandwidth of DMVR again. Cache is enabled incorrectly in DMVR process. Checking srcPadStride enables cache because srcPadStride is always 0 other than DMVR process