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Fix mem band cache enable in dmvr

Fix memory bandwidth of DMVR again. Cache is enabled incorrectly in DMVR process. Checking srcPadStride enables cache because srcPadStride is always 0 other than DMVR process

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Pipeline #1744 passed

Pipeline passed for 30e73fce on hashimry:Fix_mem_band_cache_enable_in_dmvr

Merged by Karsten SuehringKarsten Suehring 5 years ago (Jun 26, 2019 12:51pm UTC)

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Pipeline #1746 passed

Pipeline passed for 7e6c12b5 on master

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